1. Field of Invention
The present invention relates to the field of integrated electronic circuit technology. More particularly, the present invention relates to the configuration and manufacturing method of a semiconductor device using anti-fuse elements.
2. The Prior Art
A conventional anti-fuse element consists of one pair of upper and lower wiring conductor layers, and a high resistance film or an insulator film inserted between the wiring conductor layers.
An element constituted by two electrically conductive layers and an insulator film inserted between the electric-conductive layers e.g., used in Field Programmable Gate Ar rays (FPGA), is called an "anti-fuse element", because of a feature opposite to general fuse elements, such that the element functions as an insulator during regular operation and can become a connection between the conductive layers upon user activation.
At the initial state, that is the non-programmed state, the anti-fuse element functions as an insulation or high resistance, so that the pair of wirin layers has no connection at the anti-fuse element. After a predetermined destructive electric potential difference is impressed across an anti-fuse element, to create the programmed state, the portion of the wiring conductor layers and the insulator film inserted between the wiring conductor layers melts, and the conductor penetrates the fused insulator film. As a result the anti-fuse element functions as an electrical connection between the upper and lower wiring layers.
Anti-fuse elements have been used for PROMs, such as fuse ROMs and are also used for a FPGA which is a kind of Application Specific Integrated Circuit(ASIC) in recent years.
The Gate Array device has basic cells beforehand on a semiconductor substrate chip. The wirings are designed only after an order from a customer, so the device has the advantage of enabling delivery of the LSI requested by a customer in a short period of time. Since the pattern masks for wiring layers, which wiring pattern is designed on a Computer Aided Design system (CAD), are produced in response to the request of each customer, the cost for mask production per chip will tend to become expensive if the number of pieces ordered by the customer to manufacture is few. The FPGA, which has the feature that the customer can produce the wiring networks without producing his special masks, has been developed in recent years to overcome this cost problem.
The FPGA has basic cells on its chip, and wirings making lines and spaces in each two conductor layers insulated by a dielectric layer respectively, directions of wirings in respective layers are at a right angle, so that the wirings make cross stripes. The insulator layer has holes at the cross points, also referred to as lattice points, between the wiring layers and a thin insulator film is formed in the holes, namely anti-fuse elements are constituted at the cross points. The anti-fuse elements are in a non-connected state because of the thin insulator films between the wiring layers during regular use at a normal electric potential difference. When a predetermined electric potential difference is applied to the thin insulator films in the anti-fuse elements, they change to a conductive state because the upper and the lower wiring layers are connected by an irreversible dielectric breakdown. The FPGA has a tool for impressing the predetermined electric potential difference to anti-fuse elements to break the thin insulator film at arbitrary lattice points on the semiconductor chip.
After packaging the chip, a manufacturer sells them in the non-programmed state. A customer can form the connection between the wiring layers by breaking the thin insulator films of any anti-fuse elements using the tool which impresses the predetermined electric potential difference to the anti-fuse elements, and is able to realize the desired wiring by forming connections at desired anti-fuse elements.
Since the anti-fuse elements formed in the FPGA are included in a logic circuit regularly, a characteristic of such elements which provides quick operation in the circuit is needed. Thus, the characteristics of a conventional anti-fuse element are as follows:
(1) to be connected by the predetermined destructive electric potential difference impression, PA1 (2) a minimal leak current in the non-programmed state, PA1 (3) low capacitance of the anti-fuse element in the non-programmed state, and PA1 (4) low resistance of the connection in the programmed state.
It is very important to realize the good characteristics of the anti-fuse element in order to provide a useful product in the field of FPGA, as well as to build up suitable program algorithms for the anti-fuse elements.
Although many anti-fuse elements become conductive to realize a desired wiring network, namely they are changed over to the programmed state as mentioned above, there are many insulation anti-fuse elements also, that is, in the non-programmed state, which remain on the chip. The insulation anti-fuse elements electrically affect wirings as capacitances in regular use. Therefore, it is necessary to decrease not only both the resistance and the capacitance of wiring lines themselves but also both of the capacitance of the non-programmed anti-fuse elements and the resistance of the programmed anti-fuse elements, in order to realize high-speed signal propagation in the circuit.
The formation process of the conductive path in an anti-fuse element by the dielectric breakdown of the thin insulator film is explained as follows.
When a predetermined destructive electric potential difference is impressed on an anti-fuse element to connect the upper and the lower wiring layers, the current which flows inside of the thin insulator film of the anti-fuse element melts the conductive material wirings and the thin insulator film locally, and the conductive matter flows from one wiring layer toward the other by the power of the electrical field or by the impacts of the electrons along the electric potential. Since the melt point of an insulating material is higher than that of a conductive ingredient of wiring, Generally the insulating material congeals first, and one electrically conductive path of the wiring material through the thin insulator film in the anti-fuse element is formed finally. It is considered that the path of the conductor has a shape which becomes thin gradually from one wiring side toward the other wiring side where the conductive material flows out.
As shown in FIG. 13, U.S. Pat. No. 4,823,181 discloses a typical example of semiconductor apparatus having the conventional anti-fuse element. A lower wiring layer 2 is formed on a base insulator layer 11, such as a silicon oxidation layer, on a silicon semiconductor substrate 1. An insulator layer 3, such as SiO.sub.2, is formed by Chemical Vapor Deposition(CVD) on the lower wiring layer 2. A contact hole penetrates through the insulator layer 3 by a method of etching and so on, and the lower wiring 2 is exposed at the bottom of this contact hole. A dielectric anti-fuse film 4, that is a thin insulator or high resistance film, is formed on the exposed lower wiring 2 in the contact hole and on the area around it at least. An upper wiring layer 5 is formed on the insulator layer 3 and on the dielectric anti-fuse film 4. The lower wiring layer 2, the upper wiring layer 5 and the dielectric anti-fuse film 4 between them constitute a conventional anti-fuse element.
A destructive electric potential difference Von, leak current I.sub.leak and capacitance C in the non-programmed state, and resistance Ron in the programmed state are expressed as follows: EQU Von=d Eon EQU C=a.epsilon./d, EQU Ron=b .rho.d, EQU I.sub.leak =(cV/d)exp((qV/d)(.sup.(1/2))
or EQU I.sub.leak =c(V/d).sup.2 exp(V/d),
where .epsilon. is the dielectric constant of the dielectric anti-fuse film 4, .rho. is the conductivity of the conductive material of wiring layers 2 and 5, d is the thickness of the dielectric anti-fuse film, q is the unit charge, V is the electric potential difference of the regular using condition, Eon is the value of the dielectric breakdown electric field which is constant for an insulator material and a, b, c are constants.
Because the above values are wholly dependent on the thickness d of the dielectric anti-fuse film 4, it is difficult to vary each characteristic value independently, and it is very difficult to make all values suitable since the dependences for the values are different mutually. For example, when the thickness of the dielectric anti-fuse film 4 is increased to decrease the leak current, the resistance in the programmed state and the destructive electric potential difference increase although the capacitance in the non-programmed state decreases. Since the anti-fuse element has the above-mentioned characteristics there is only one fundamental solution to realize the ideal anti-fuse element having all of the desirable destructive electric potential difference, the low resistance in the programmed state, and the low capacitance and no leak current in the non-programmed state. That solution is to change the material of the dielectric anti-fuse film.
Moreover, the wiring design requires a lot of choices generally since logic devices have very complex wiring networks. The aforementioned configuration of the anti-fuse element has a problem that is to restrict the wiring design because the anti-fuse element must use two-layer wiring.
In the aforementioned example, the dielectric anti-fuse film in the anti-fuse element for the FPGA consists of amorphous silicon film or nitride silicon film or metal oxidation film or SiO.sub.2 +Si.sub.3 N.sub.4 film (ON film) or SiO.sub.2 +Si.sub.3 N.sub.4 +SiO.sub.2 film (ONO film) and so on. In a case of using ON film or ONO film for the anti-fuse elements, there is required a process of heat oxidation or heat nitriding in order to form a suitable anti-fuse insulator film. Since such a formation process for a suitable anti-fuse film requires raisins the temperature of the environment to about 700-1000 degrees centigrade generally, the manufacturer must choose only special materials which have respective high melt points so as not to melt in the formation process at the high temperature. As a result, the electrodes and wirings placed under the anti-fuse elements can not consist of aluminum which can not bear such an elevated high temperature, and a polycrystalline silicon doped impurity is used instead of aluminum usually. When the conductive path in the anti-fuse element is made from polycrystalline silicon in such a case that both of the upper and the lower wiring layers are formed with polycrystalline silicon, or that only the lower wiring is formed with polycrystalline silicon and the electric field which carries the material from the lower wiring layer toward the upper side makes the dielectric breakdown in the anti-fuse element, the resistance of the path in the anti-fuse element becomes considerably higher (several kilo-ohms) than that of metal (100 ohms typically).
Even if the wirings of upper- and lower-side layers are formed with metal, such as aluminum, when the dielectric anti-fuse film is thick, for example, the thickness of the dielectric anti-fuse film made from amorphous silicon with the method of sputtering becomes about 200 nm, the conductive path created by the dielectric breakdown has the shape becoming thinner along the flowing direction, so that the resistance of the anti-fuse element increases.
Generally, it is required for an anti-fuse element having a specification from customers that the leakage current and the capacitance in the insulating state (the non-programmed state) and the resistance after dielectric breakdown of the dielectric anti-fuse film (in the programmed state) are below predetermined values during normal operation. The specification of these predetermined values also serves to predetermine destructive electric potential difference.
As mentioned above, the conventional anti-fuse element has a first problem that it is difficult to furnish all of the desired destructive electric potential difference to program, low resistance in the programmed state, low capacitance and low leakage current in the non-programmed state at the same time. Second, the degree of freedom for wiring designing is restricted because of the configuration of the two wiring layers to constitute the lattice. It is very important to make the resistance of the anti-fuse element in the programmed state and the capacitance in the non-programmed state smaller in order to operate a logic circuit in the FPGA at high speed.